Semiconductors
Design for Test
We implement robust DFT strategies that guarantee high-quality, fully functional chips, ready for the market.
We understand that DFT is essential for achieving the highest chip quality and reliability levels. Our solutions ensure faster test times, improved fault detection, and higher production yield.
At AstraSilica, we recognize that Design for Test (DFT) is not a last-minute addition but an integral part of the design process itself. Our expert DFT engineers work hand-in-hand with your design team from the initial concept, strategically weaving testability into the very fabric of your chip.
Our meticulous approach to DFT delivers tangible results: higher test coverage that leaves no room for hidden defects, reduced test costs through optimized test time and resource allocation, and ultimately, a significantly improved production yield that translates into a more successful and cost-effective product launch for you.
We go beyond the limitations of traditional scan-based methods, embracing a sophisticated toolkit of advanced DFT techniques. At AstraSilica, we don’t just test chips; we design them for testability, ensuring quality and reliability are woven into every layer of your semiconductor innovation.
Scan Implementation with and without Compression
- Implementation of Hierarchical and Flat Scan for Small and Multi-million Gates Design
- LBIST Implementation and Spyglass at RTL Level
- LEC for Scan Netlist
- IJTAG Implementation at Block and SOC Level
ATPG Pattern Generation for Different Fault Models
- ATPG Pattern Generation for Stuck-at, Transition, Bridging and Cell aware Fault Model and Extensive Coverage Analysis at Block Level and SOC Level
- Low Power Pattern Generation, Pattern Optimization and TPI Analysis
- Pattern Retargeting at SOC Level
Post Silicon Debug and ATE Support
- Post Silicon Support and ATE Bring up
- ATE Board Design and Bring up
- Test Program Development and Testing in different types of testers like Advantest 93K and Production support
Memory Testing using MBIST Implementation
- MBIST Implementation with and without repair
- Simulation and Debug at Timing and No-timing Simulations
IO Testing using JTAG/BSCAN Implementation
- Implementation of Boundary Scan at SOC Level
- Expertise in IEEE1149.1 and IEEE1149.6 Standards
DFT Architecture and Implementation
- Flow and Methodology Development
DFT Validation
- Simulations at Timing and No-timing
- DFX Validation at RTL and Gate Level
- Analog BIST Simulations
